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makegapedcells desativa rowcolor

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makegapedcells desativa rowcolor

Eu tenho a seguinte tabela

\documentclass[a4paper, 11pt, parskip]{scrreprt}
\usepackage{graphicx}
\usepackage{colortbl}
\usepackage{xcolor}
\usepackage{multirow}
\usepackage{makecell}%To keep spacing of text in tables
\setcellgapes{3pt}%parameter for the spacing

\newcommand{\specialcell}[2][c]{%
    \begin{tabular}[#1]{@{}c@{}}#2\end{tabular}}

\begin{document}
\begin{table}[h]
    %\makegapedcells
    \centering
    \resizebox{\textwidth}{!}{%resizing the whole table
        \begin{tabular}{|c|c|c|c|c|c|c|c|c|}
            \hline 
            \multicolumn{9}{|c|}{\Huge Relaisplatine} \\ 
            \hline 
            Relay Nr. & Part & Test-Id & \specialcell[c]{Signal-Name \\for Testcases} & Conn. & Pin & \specialcell[c]{Pin-\\Func.} & R Value & \specialcell[c]{Influenced \\ Signal/Voltage } \\ 
            \hline
            \rowcolor[gray]{0.8} 
            &  &  &  &  & 1 & N.C. & Open & Open \\
            \cline{6-9}
            %\hline 
            0 & WFB & WFB\_VOLT\_SDAR & WFB\_CLOCK\_+1V8 & P2 & 3 & COM &  0 $\Omega$ & SIGN02659 \\
            \cline{6-9}  
            %\hline 
            &  &  &  &  & 5 & N.O. &  0 $\Omega$ & GND \\
            %\cline{6-9}  
            \hline 
            &  &  &  &  & 7 & N.C. &  Open & Open \\ 
            \cline{6-9} 
            1 & WFB & WFB\_CLK & WFB\_CLKDIS153\_MUXOUT  & P2 & 9 & COM &  0 $\Omega$ & P5801 \\ 
            \cline{6-9}
            &  &  &  &  & 11 & N.O. &  0 $\Omega$ & P5802 \\ 
            \hline 
            &  &  &  &  & 13 & N.C. &  Open & Open \\ 
            \cline{6-9} 
            2 & WFB & WFB\_VOLT\_SDAR & WFB\_WF\_FPGA\_VCORE & P2 & 15 & COM &  0 $\Omega$ & SIGN02652 \\ 
            \cline{6-9} 
            &  &  &  &  & 17 & N.O. &  0 $\Omega$ & GND \\ 
            \hline 
            &  &  &  &  &  & N.C. &  Open & Open \\ 
            \cline{6-9} 
            3 & RIO & RIO\_T2\_DATA & RIO\_T2\_DATA & P3 & PCB-Cable & COM &  0 $\Omega$ & RIO\_GPP\_I2C\_SDA \\ 
            \cline{6-9} 
            &  &  &  &  & PCB-Cable & N.O. &  0 $\Omega$ & GND \\ 
            \hline 
            &  &  &  &  &  & N.C. &  Open & Open \\ 
            \cline{6-9} 
            4 &  &  &  & P3 &  & COM &  0 $\Omega$ &  \\ 
            \cline{6-9} 
            &  &  &  &  & PCB-Cable & N.O. &  0 $\Omega$ & GND \\ 
            \hline 
            &  &  &  &  & 14 & N.C. &  Open & Open \\ 
            \cline{6-9} 
            5 & RIO & RIO\_T1\_CLK & RIO\_T1\_CLK & P2 & 16 & COM &  0 $\Omega$ & RIO\_GPP\_I2C\_SCL1 \\ 
            \cline{6-9} 
            &  &  &  &  & 18 & N.O. &  0 $\Omega$ &  \\ 
            \hline 
            &  &  &  &  & 8 & N.C. &  Open & Open \\ 
            \cline{6-9} 
            6 & WFB & WFB\_VOLT\_SDAR & WFB\_WF\_FPGA\_MGTVCCAUX & P2 & 10 & COM &  0 $\Omega$ & SIGN02672 \\ 
            \cline{6-9} 
            &  &  &  &  & 12 & N.O. &  0 $\Omega$ &  \\ 
            \hline 
            &  &  &  &  & 2 & N.C. &  Open & Open \\ 
            \cline{6-9} 
            7 & WFB & WFB\_VOLT\_SDAR & WFB\_WF\_FPGA\_AVTT & P2 & 4 & COM &  0 $\Omega$ & SIGN02661 \\ 
            \cline{6-9} 
            &  &  &  &  & 6 & N.O. &  0 $\Omega$ & Open \\ 
            \hline 
        \end{tabular}
    }
    \caption{Verkabelung der ersten Relaisplatine an X400/PortA}
\end{table}
\end{document}

insira a descrição da imagem aqui

Como você pode ver o título da tabela, denominado Relaisplatine, está tocando as bordas da tabela. Para resolver esse problema eu usei \makegapedcells, mas se eu usar ele desativa a coloração da linha.

Como posso fazer com que o título não toque nas bordas e tenha linhas coloridas?

Responder1

A macro \makegapedcellsdo pacote makecellnão é compatível com a coloração da tabela. Em casos semelhantes, você pode usar pacote cellspacee extensão Spara tipos de coluna, onde deseja adicionar espaços verticais às células:

\documentclass[a4paper, 11pt, parskip]{scrreprt}
\usepackage[table]{xcolor}
\usepackage{cellspace, makecell, multirow}% for tables
\setlength\cellspacetoplimit{4pt}
\setlength\cellspacebottomlimit{4pt}

%-------------------------------------- only for show page layout
\usepackage{showframe}
\renewcommand\ShowFrameLinethickness{0.15pt}
\renewcommand*\ShowFrameColor{\color{red}}
%---------------------------------------------------------------%

\begin{document}
\begin{table}%[ht]
    \tiny
    \setlength\tabcolsep{3pt}
    \centering
        \begin{tabular}{|c|c|c|c|c|c|Sc|c|c|}
            \hline
            \multicolumn{9}{|>{\normalsize}Sc|}{Relaisplatine} \\
            \hline
\makecell{Relay\\ Nr.} & Part & Test-Id & \makecell[c]{Signal-Name \\for Testcases} & Conn. & Pin & \makecell[c]{Pin-\\Func.} & R  & \makecell[c]{Influenced \\ Signal/Voltage } \\
            \hline
            \rowcolor[gray]{0.8}
            &  &  &  &  & 1 & N.C. & Open & Open \\
            \cline{6-9}
            %\hline
            0 & WFB & WFB\_VOLT\_SDAR & WFB\_CLOCK\_+1V8 & P2 & 3 & COM &  0 $\Omega$ & SIGN02659 \\
            \cline{6-9}
            %\hline
            &  &  &  &  & 5 & N.O. &  0 $\Omega$ & GND \\
            %\cline{6-9}
            \hline
            &  &  &  &  & 7 & N.C. &  Open & Open \\
            \cline{6-9}
            1 & WFB & WFB\_CLK & WFB\_CLKDIS153\_MUXOUT  & P2 & 9 & COM &  0 $\Omega$ & P5801 \\
            \cline{6-9}
            &  &  &  &  & 11 & N.O. &  0 $\Omega$ & P5802 \\
            \hline
            &  &  &  &  & 13 & N.C. &  Open & Open \\
            \cline{6-9}
            2 & WFB & WFB\_VOLT\_SDAR & WFB\_WF\_FPGA\_VCORE & P2 & 15 & COM &  0 $\Omega$ & SIGN02652 \\
            \cline{6-9}
            &  &  &  &  & 17 & N.O. &  0 $\Omega$ & GND \\
            \hline
            &  &  &  &  &  & N.C. &  Open & Open \\
            \cline{6-9}
            3 & RIO & RIO\_T2\_DATA & RIO\_T2\_DATA & P3 & PCB-Cable & COM &  0 $\Omega$ & RIO\_GPP\_I2C\_SDA \\
            \cline{6-9}
            &  &  &  &  & PCB-Cable & N.O. &  0 $\Omega$ & GND \\
            \hline
            &  &  &  &  &  & N.C. &  Open & Open \\
            \cline{6-9}
            4 &  &  &  & P3 &  & COM &  0 $\Omega$ &  \\
            \cline{6-9}
            &  &  &  &  & PCB-Cable & N.O. &  0 $\Omega$ & GND \\
            \hline
            &  &  &  &  & 14 & N.C. &  Open & Open \\
            \cline{6-9}
            5 & RIO & RIO\_T1\_CLK & RIO\_T1\_CLK & P2 & 16 & COM &  0 $\Omega$ & RIO\_GPP\_I2C\_SCL1 \\
            \cline{6-9}
            &  &  &  &  & 18 & N.O. &  0 $\Omega$ &  \\
            \hline
            &  &  &  &  & 8 & N.C. &  Open & Open \\
            \cline{6-9}
            6 & WFB & WFB\_VOLT\_SDAR & WFB\_WF\_FPGA\_MGTVCCAUX & P2 & 10 & COM &  0 $\Omega$ & SIGN02672 \\
            \cline{6-9}
            &  &  &  &  & 12 & N.O. &  0 $\Omega$ &  \\
            \hline
            &  &  &  &  & 2 & N.C. &  Open & Open \\
            \cline{6-9}
            7 & WFB & WFB\_VOLT\_SDAR & WFB\_WF\_FPGA\_AVTT & P2 & 4 & COM &  0 $\Omega$ & SIGN02661 \\
            \cline{6-9}
            &  &  &  &  & 6 & N.O. &  0 $\Omega$ & Open \\
            \hline
        \end{tabular}
    \caption{Verkabelung der ersten Relaisplatine an X400/PortA}
\end{table}
\end{document}

Em vez disso specialcell(não definido no seu MWE) eu uso o padrão \makecell{...}do pacote `makecell}.

insira a descrição da imagem aqui

No MWE acima eu removo \resizebox{\textwidth}{!}{%resizing the whole table ...}, pois dá o mesmo efeito que alterar o tamanho da fonte para \tiny. Isto pode ser um problema sério para os leitores, uma vez que o texto é muito pequeno para uma leitura normal (veja meu comentário acima).

Termo aditivo: Caso você considere rotacionar sua mesa, veja se o seguinte sMWE pode te ajudar. Observe que mesmo nela e com tamanho de fonte reduzido para \small, a largura da tabela é maior que a altura do texto:

\documentclass[a4paper, 11pt, parskip]{scrreprt}
\usepackage{rotating}
\usepackage[table]{xcolor}
\usepackage{cellspace, makecell, multirow}% for tables
\setlength\cellspacetoplimit{3pt}       % additional top vertical spaces in cells
\setlength\cellspacebottomlimit{3pt}    % additional bottom vertical spaces in cells

%-------------------------------------- only for show page layout
\usepackage{showframe}
\renewcommand\ShowFrameLinethickness{0.15pt}
\renewcommand*\ShowFrameColor{\color{red}}
%---------------------------------------------------------------%

\begin{document}
    \begin{sidewaystable}
    \centering
    \small
\begin{tabular}{|c|c|c|c|c|c|Sc|c|c|}% added S foractivate additional vertical spaces in cels
    \hline
\multicolumn{9}{|Sc|}{Relaisplatine} \\
    \hline
\makecell{Relay\\ Nr.} & Part & Test-Id & \makecell[c]{Signal-Name \\for Testcases} & Conn. & Pin & \makecell[c]{Pin-\\Func.} & R  & \makecell[c]{Influenced \\ Signal/Voltage }        \\
    \hline
\rowcolor[gray]{0.8}
&  &  &  &  & 1 & N.C. & Open & Open \\
    \cline{6-9}
0 & WFB & WFB\_VOLT\_SDAR & WFB\_CLOCK\_+1V8 & P2 & 3 & COM &  0 $\Omega$ & SIGN02659 \\
    \cline{6-9}
&  &  &  &  & 5 & N.O. &  0 $\Omega$ & GND \\
    \hline
&  &  &  &  & 7 & N.C. &  Open & Open \\
    \cline{6-9}
1 & WFB & WFB\_CLK & WFB\_CLKDIS153\_MUXOUT  & P2 & 9 & COM &  0 $\Omega$ & P5801 \\
    \cline{6-9}
&  &  &  &  & 11 & N.O. &  0 $\Omega$ & P5802 \\
    \hline
&  &  &  &  & 13 & N.C. &  Open & Open \\
    \cline{6-9}
2 & WFB & WFB\_VOLT\_SDAR & WFB\_WF\_FPGA\_VCORE & P2 & 15 & COM &  0 $\Omega$ & SIGN02652 \\
    \cline{6-9}
&  &  &  &  & 17 & N.O. &  0 $\Omega$ & GND \\
    \hline
&  &  &  &  &  & N.C. &  Open & Open \\
    \cline{6-9}
3 & RIO & RIO\_T2\_DATA & RIO\_T2\_DATA & P3 & PCB-Cable & COM &  0 $\Omega$ & RIO\_GPP\_I2C\_SDA \\
    \cline{6-9}
&  &  &  &  & PCB-Cable & N.O. &  0 $\Omega$ & GND \\
    \hline
&  &  &  &  &  & N.C. &  Open & Open \\
    \cline{6-9}
4 &  &  &  & P3 &  & COM &  0 $\Omega$ &  \\
    \cline{6-9}
&  &  &  &  & PCB-Cable & N.O. &  0 $\Omega$ & GND \\
    \hline
&  &  &  &  & 14 & N.C. &  Open & Open \\
    \cline{6-9}
5 & RIO & RIO\_T1\_CLK & RIO\_T1\_CLK & P2 & 16 & COM &  0 $\Omega$ & RIO\_GPP\_I2C\_SCL1 \\
    \cline{6-9}
&  &  &  &  & 18 & N.O. &  0 $\Omega$ &  \\
    \hline
&  &  &  &  & 8 & N.C. &  Open & Open \\
    \cline{6-9}
6 & WFB & WFB\_VOLT\_SDAR & WFB\_WF\_FPGA\_MGTVCCAUX & P2 & 10 & COM &  0 $\Omega$ & SIGN02672 \\
    \cline{6-9}
&  &  &  &  & 12 & N.O. &  0 $\Omega$ &  \\
    \hline
&  &  &  &  & 2 & N.C. &  Open & Open \\
    \cline{6-9}
7 & WFB & WFB\_VOLT\_SDAR & WFB\_WF\_FPGA\_AVTT & P2 & 4 & COM &  0 $\Omega$ & SIGN02661 \\
    \cline{6-9}
&  &  &  &  & 6 & N.O. &  0 $\Omega$ & Open \\
    \hline
\end{tabular}
\caption{Verkabelung der ersten Relaisplatine an X400/PortA}
    \end{sidewaystable}
\end{document}

Responder2

Você {NiceTabular}tem nicematrixuma chave cell-space-limitscompatível com \rowcolor.

\documentclass[a4paper, 11pt, parskip]{scrreprt}
\usepackage{xcolor}
\usepackage{nicematrix}

\begin{document}
\begin{table}%[ht]
    \tiny
    \setlength\tabcolsep{3pt}
    \centering
        \begin{NiceTabular}{|c|c|c|c|c|c|c|c|c|}[colortbl-like,cell-space-limits=4pt]
            \hline
            \Block{1-9}{\normalsize Relaisplatine} \\
            \hline
\Block{}{Relay\\ Nr.} & Part & Test-Id & \Block{}{Signal-Name \\for Testcases} & Conn. & Pin & \Block{}{Pin-\\Func.} & R  & \Block{}{Influenced \\ Signal/Voltage } \\
            \hline
            \rowcolor[gray]{0.8}
            &  &  &  &  & 1 & N.C. & Open & Open \\
            \cline{6-9}
            0 & WFB & WFB\_VOLT\_SDAR & WFB\_CLOCK\_+1V8 & P2 & 3 & COM &  0 $\Omega$ & SIGN02659 \\
            \cline{6-9}
            &  &  &  &  & 5 & N.O. &  0 $\Omega$ & GND \\
            \hline
            &  &  &  &  & 7 & N.C. &  Open & Open \\
            \cline{6-9}
            1 & WFB & WFB\_CLK & WFB\_CLKDIS153\_MUXOUT  & P2 & 9 & COM &  0 $\Omega$ & P5801 \\
            \cline{6-9}
            &  &  &  &  & 11 & N.O. &  0 $\Omega$ & P5802 \\
            \hline
            &  &  &  &  & 13 & N.C. &  Open & Open \\
            \cline{6-9}
            2 & WFB & WFB\_VOLT\_SDAR & WFB\_WF\_FPGA\_VCORE & P2 & 15 & COM &  0 $\Omega$ & SIGN02652 \\
            \cline{6-9}
            &  &  &  &  & 17 & N.O. &  0 $\Omega$ & GND \\
            \hline
            &  &  &  &  &  & N.C. &  Open & Open \\
            \cline{6-9}
            3 & RIO & RIO\_T2\_DATA & RIO\_T2\_DATA & P3 & PCB-Cable & COM &  0 $\Omega$ & RIO\_GPP\_I2C\_SDA \\
            \cline{6-9}
            &  &  &  &  & PCB-Cable & N.O. &  0 $\Omega$ & GND \\
            \hline
            &  &  &  &  &  & N.C. &  Open & Open \\
            \cline{6-9}
            4 &  &  &  & P3 &  & COM &  0 $\Omega$ &  \\
            \cline{6-9}
            &  &  &  &  & PCB-Cable & N.O. &  0 $\Omega$ & GND \\
            \hline
            &  &  &  &  & 14 & N.C. &  Open & Open \\
            \cline{6-9}
            5 & RIO & RIO\_T1\_CLK & RIO\_T1\_CLK & P2 & 16 & COM &  0 $\Omega$ & RIO\_GPP\_I2C\_SCL1 \\
            \cline{6-9}
            &  &  &  &  & 18 & N.O. &  0 $\Omega$ &  \\
            \hline
            &  &  &  &  & 8 & N.C. &  Open & Open \\
            \cline{6-9}
            6 & WFB & WFB\_VOLT\_SDAR & WFB\_WF\_FPGA\_MGTVCCAUX & P2 & 10 & COM &  0 $\Omega$ & SIGN02672 \\
            \cline{6-9}
            &  &  &  &  & 12 & N.O. &  0 $\Omega$ &  \\
            \hline
            &  &  &  &  & 2 & N.C. &  Open & Open \\
            \cline{6-9}
            7 & WFB & WFB\_VOLT\_SDAR & WFB\_WF\_FPGA\_AVTT & P2 & 4 & COM &  0 $\Omega$ & SIGN02661 \\
            \cline{6-9}
            &  &  &  &  & 6 & N.O. &  0 $\Omega$ & Open \\
            \hline
        \end{NiceTabular}
    \caption{Verkabelung der ersten Relaisplatine an X400/PortA}
\end{table}
\end{document}

Você precisa de várias compilações (porque nicematrixusa PGF/Tikz nos bastidores).

Saída do código acima

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